1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit devices having series-connected field effect transistors (FETs) and, more specifically, to an integrated circuit device, such as a radio frequency (RF) switch, having series-connected planar or non-planar FETs and integrated voltage equalization.
2. Description of the Related Art
Integrated circuit design decisions are often driven by device scalability and manufacturing efficiency.
For example, because size scaling of planar field effect transistors (FETs) resulted in reduced drive current as a function of reduced channel width, multi-gate non-planar field effect transistors (MUGFETs) (e.g., dual-gate FETs and tri-gate FETs) were developed to provide scaled devices with increased drive current and reduced short channel effects. Dual-gate FETs (also referred to as fin-type FETs or FINFETs) are non-planar FETs in which a fully depleted channel region is formed in the center of a relatively thin semiconductor fin with source and drain regions in the opposing ends of the fin adjacent to the channel region. A gate is formed over the top surface and on each side of the thin fin in an area corresponding to the channel region to provide two-dimensional field effects. A dielectric cap layer (such as a nitride cap layer) typically isolates the top surface of the channel region from the gate so that only two-dimensional field effects are exhibited. The effective channel width is determined by the fin height. Additionally, a fin thickness of approximately one-half (or less) the length of the gate can ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. Tri-gate FETs are similar in structure to FINFETs, except that the fin of a tri-gate FET is wider and devoid of a dielectric cap layer. Thus, the gate, which is formed over the top surface and on each side of the fin, causes three-dimensional field effects to be exhibited. Typically, the fin height to width ratio in a tri-gate FET is in the range of 3:2 to 2:3 so that the channel will remain fully depleted and so that the resulting three-dimensional field effects will provide greater device drive current and improved short-channel characteristics over a planar transistor. The effective channel width of MUGFETs and, thereby, the device drive current can be increased by using multiple semiconductor fins.
Additionally, because size scaling of field effect transistors (FETs), including both planar FETs and non-planar FETs, has resulted in limits on the maximum source-to-drain voltage that any single FET can reliably switch, FET networks with multiple series-connected FETs were developed in order to support the switching of higher source-to-drain voltages. In such FET networks, the series-connected FETs are also often connected in parallel to a discrete voltage distribution network in order to ensure uniform voltage distribution and, thereby to avoid breakdown run-away, when the FETs are in the off-state, and have a large voltage across the entire series network of FETs.